DS1234 conditional nonvolatile controller chip DS1234 021798 1/7 features ? converts cmos static rams into nonvolatile memories ? software-controlled write inhibit ? software-controlled battery disconnect extends battery life ? unconditionally write protects when v cc is out of tolerance ? consumes less than 100 na of battery current ? power fail signal can be used to interrupt processor on power failure ? low forward voltage drop on the v cc switch ? optional 16-pin soic surface mount package pin assignment gnd vcci vbat nc a3 a2 a1 a0 weo ceo nc nc vcco vcci vbat vcco DS1234 14-pin dip (300 mil) see mech. drawings section DS1234s 16-pin soic (300 mil) see mech. drawings section pf cei wei a3 a1 a0 pf a2 gnd weo ceo nc cei wei 1 2 3 4 5 6 7 14 13 12 11 10 9 8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 pin description v cco ram supply nc no connection cei chip enable input wei write enable input ceo chip enable output to ram weo write enable output to ram gnd ground pf power fail output a0-a3 address inputs v bat battery input v cci +5v supply description the DS1234 is a cmos circuit that converts cmos ram into nonvolatile memory and adds two software selectable switches. incoming power is monitored for an out-of-tolerance condition. when such a condition is detected, chip enable and write enable to the ram are inhibited to accomplish write protection, and the battery is switched on to supply the memory with uninterrupted power. the two software selectable switches provided by the DS1234 are capable of inhibiting both the write enable to the ram and the battery backup circuitry by a pattern recognition sequence across four address lines. inhibiting the write enable to the nonvolatile ram pro- vides data integrity by isolating the memory contents from external change. the second switch provides add- ed flexibility and increases battery life to the system by enabling/disabling the battery for shipment or storage, or when battery backup is not needed.
DS1234 021798 2/7 operation the DS1234 conditional nonvolatile controller per- forms three circuit functions required to battery back up a ram. first, a switch is provided to direct power from the battery or the incoming supply (v cci ), depending on which is greater. this switch has a voltage drop of less than 0.2v. the second function is power fail detection. the DS1234 constantly monitors the incoming supply. when the supply goes out-of-tolerance, a comparator detects power fail and inhibits chip enable and write en- able. the threshold voltage, v tp , at which power fail is detected is defined as 1.26 times v bat . the third func- tion of write protection is accomplished by holding the ceo and weo output signals to within 0.2 volts of the v cci or battery supply. in addition to the nonvolatile controller functions, the DS1234 supplies two software-selectable switches for master control of the write enable and the nonvolatile controller itself. the switches are controlled by a 16-cycle pattern recognition sequence across four ad- dress lines (see tables 1 and 2). prior to entering the pattern recognition sequence that will define the two switch settings, a read cycle of 1111 on address inputs a0 through a3 should be executed to initialize the com- pare pointer of clock zero. each four-bit compare word is clocked into the DS1234 on the negative edge of cei . a0, a1 and a2 must match the compare pattern on all 16 consecutive cycles while a3 must match only the first eleven; the last five are used to define the switch set- tings. the eleventh address cycle, starting at zero, de- fines the switch that inhibits the write enable to the ram (weo ). a logic one in this location allows read/write op- erations so that weo will follow wei and data can be updated. a zero on cycle eleven turns the ram into a read-only memory (rom). the next four address cycles, 12 thorough 15, define whether the nonvolatile controller operation is enabled or disabled. a bit pattern of 1010 activates the nonvolatile controller; data in the ram is maintained on power loss. any pattern other than 1010 will disable the nonvolatile controller opera- tion. at the completion of the 16th cycle, if the pattern recog- nition sequence is correct, the switch settings defined in cycles 11 though 15 are transferred and are active for the next memory cycle. when external battery power is applied for the first time, the DS1234 will come up with the nonvolatile controller off. upon initial v cc power, the write enable will be set in read/write operation (wei =weo ). controller to memory interface figure 1 v cc ce we a n a 3 a 2 a 1 a 0 cmos ram 1 5 6 8 13 v cco ceo weo pf to write protect oth- er memories v bat + DS1234 +5v 3 4 9 14 12 11 10 v cci cei wei a 3 a 2 a 1 a 0 from decoder ce we 4 n address bus
DS1234 021798 3/7 address input pattern table 1 cycle number address inputs 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 a3 1 0 1 0 0 0 1 1 0 1 0 * * * * * a2 0 1 0 1 1 1 0 0 1 0 1 0 0 0 1 1 a1 1 0 1 0 0 0 1 1 0 1 0 1 1 1 0 0 a0 0 1 0 1 1 1 0 0 1 0 1 0 0 0 1 1 control select table 2 wei battery control operation 11 12 13 14 15 0 x x x x read only operation 1 x x x x read/write operation x 1 0 1 0 enables nonvolatile controller* x = don't care *any other combination turns controller off
DS1234 021798 4/7 absolute maximum ratings* voltage on any pin relative to ground -0.3v to +7.0v operating temperature 0 c to 70 c storage temperature -55 c to +125 c soldering temperature 260 c for 10 seconds * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. recommended dc operating conditions (0 c to 70 c) parameter symbol min typ max units notes power supply voltage v cci 4.5 5.0 5.5 v 1 input high voltage v ih 2.2 v cc +0.3 v 1 input low voltage v il -0.3 +0.8 v 1 battery voltage v bat 2.5 3.5 v dc electrical characteristics (0 c to 70 c; v cci =5v 10%) parameter symbol min typ max units notes supply current i cci 5 ma 2 supply current @ v cco = v cci - 0.2 i cco 80 ma 3 input leakage i il -1.0 +1.0 m a output leakage i lo -1.0 +1.0 m a output current @ 2.4v i oh -1.0 ma 4 output current @ 0.4v i ol 4.0 ma 4 (0 c to 70 c; v cci =< v bat ) ceo , weo output v ohl v bat -0.2 v 6 battery current i bat 0.1 m a 7 battery backup current @ v cco = v bat - 0.3v i cco1 100 m a 5
DS1234 021798 5/7 capacitance (t a =25 c) parameter symbol min typ max units notes input capacitance c in 5 pf output capacitance c ou 7 pf ac electrical characteristic (0 c to 70 c; v cci = 5v 10%) parameter symbol min typ max units notes address setup t as 0 ns address hold t ah 50 ns read recovery t rr 40 ns cei pulse width t cw 110 ns propagation delay t pd 20 ns (0 c to 70 c; v cci < v tp ) recovery at power up t rec 2 ms v cc slew rate power down t f 10 m s v cc slew rate power up t r 0 m s cei high to power fail t pf 0 ns
DS1234 021798 6/7 timing diagram: switch setting bit 15 a0a3 ceo weo cei wei t as t aw t cw t rr t pd t pd t pd timing diagram: power down v bat - 0.2 v t pf t pd t pd v ih v il v ih v il t f v bat v tp v cci wei , cei weo , ceo
DS1234 021798 7/7 timing diagram: power-up v bat -0.2v v ih v ih v il v tp t pd t rec v cci wei , cei weo , ceo v bat t r notes: 1. all voltages are referenced to ground. 2. measured with v cco , ceo and weo open. 3. i cco is the maximum average load that the DS1234 can supply to the memories. 4. measured with a load as shown in figure 2. 5. i cc01 is the maximum average load current that the DS1234 can supply to the memories in the battery back- up mode. 6. ceo and weo , outputs can only sustain leakage current in the battery backup mode. 7. i bat is the total load current that the DS1234 uses from the battery input pin with v cco , ceo , and weo open. output load figure 2 50pf +5 volts 1.1k 680 d.u.t.
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